FEATURES
Arm® Cortex®-M23 without TrustZone®
 Arm® Cortex®-M23 processor, running up to 48 MHz when VDD = 1.75V ~ 5.5V
 Built-in PMSAv8 Memory Protection Unit (MPU)
 Built-in Nested Vectored Interrupt Controller (NVIC)
 32-bit Single-cycle hardware multiplier and 32-bit 17-cycle hardware divider
 24-bit system tick timer
 Supports Programmble and maskable interrupt
 Supports Low Power Sleep mode by WFI and WFE instructions
 Supports single cycle I/O access
 Supports XOM feature with 1 region

Low power mode and current
 Low Power mode:
– Idle mode
 Power-down mode (PD)
– Fast Wake-up Power-down mode (FWPD)
– Deep Power-down mode (DPD)

Wake-up source and wakeup time
 EINT, Touch key, USCI, RTC, WDT, I2C, Timer, UART, BOD, LVR, POR, GPIO, USBD, ACMP, Debug interface, NMI and Reset pin from Power-down mode or Fast Wake-up Power-down mode
 RTC, Wake-up Timer, LVR, Wake-up pins, from Deep Power-down mode

Power supply and low voltage detect
 Built-in LDO for wide operating voltage from 1.75V to 5.5V
 Core power voltage: 1.5V
 Brown-out detector
– With 7 levels: 4.4V/3.7V/3.0V/2.7V/2.4V/2.0V/1.8V
– Supports Brown-out Interrupt and Reset option
 Low Voltage Reset
– Threshold voltage levels: 1.55V

Cyclic Redundancy Calculation Unit
 Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
 Programmable order reverse setting for input data and CRC checksum
 Programmable 1’s complement setting for input data and CRC
checksum.
 Supports 8-/16-/32-bit of data width
 Programmable seed value
 8-bit write mode: 1-AHB clock cycle operation
 16-bit write mode: 2-AHB clock cycle operation
 32-bit write mode: 4-AHB clock cycle operation
 Supports using PDMA to write data to perform CRC operation

Security
 96-bit Unique ID (UID)
 128-bit Unique Customer ID (UCID)
 AES-128, 192, 256

-Memories
Flash
 Up to 256 KB application ROM (APROM)
 4 KB Flash for user program loader (LDROM)
 Up to 48 MHz with zero wait state for consecutive address read access
 12 bytes User Configuration Block to control system initiation.
 512B page erase for all embedded Flash
 32-bit and multi-word Flash programming function.
 Supports In-System-Programming (ISP), In-Application-Programming (IAP) update embedded Flash memory
 Supports CRC-32 checksum calculation function
 Supports Flash all one verification function (hardware can check page erase verify)
 Hardware external read protection of whole Flash memory by Security Lock Bit
 Supports XOM feature with 1 region

SRAM
 Up to 32 KB embedded SRAM
 Supports byte-, half-word- and word-access
 Supports PDMA mode

Peripheral DMA (PDMA)
 Up to 8 independent configurable channels for automatic data transfer between memories and peripherals
 Channel 0, 1 support time-out function
 Basic and Scatter-Gather Transfer modes
 Each channel supports circular buffer management using Scatter-Gather Transfer mode
 Two types of priorities modes: Fixed-priority and Round-robin modes
 Transfer data width of 8, 16, and 32 bits
 Single and burst transfer type
 Source and destination address can be increment or fixed
 PDMA transfer count up to 65536
 Request source can be form software, SPI/I2S, I2C, UART, USCI, EADC, DACand TIMER

Clocks
Clock Source
 Built-in 4.032 MHz internal high speed RC oscillator (MIRC) for system operation
 Built-in 48 MHz internal high speed RC oscillator (HIRC) for system operation
 Built-in 38.4 kHz internal low speed RC oscillator (LIRC) for Watchdog Timer and wake-up operation.
 Built-in 4~32 MHz external high speed crystal oscillator (HXT) for precise timing operation
 Built-in 32.768 kHz external low speed crystal oscillator (LXT) for RTC function and low-power system operation
 Supports clock on-the-fly switch
 Supports clock failure detection for high/low speed external crystal oscillator
 HXT clock frequency accuracy detector
 Supports exception (NMI) generated once a clock failure detected
 Supports divided clock output

Timers
32-bit Timer
TIMER mode
 4 sets of 32-bit timers with 24-bit up counters and 8-bit prescale counters
 Independent clock source for each timer
 One-shot, Periodic, Toggle and Continuous Counting operation modes
 Event counting function to count the event from external pin
 Input capture function to capture or reset counter value
 External capture pin event for interval measurement.
 External capture pin event to reset 24-bit up counter.
 Chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated
 Timer interrupt flag or external capture interrupt flag to trigger BPWM, EADC, DAC and PDMA.
 Internal capture triggered source from ACMP output.
 Inter-Timer trigger capture mode
PWM mode
 16-bit compare register and period register
 Double buffer for period register and compare register
 Supports inverse in PWM output
 PWM interrupt wake-up from system Power-down mode

BPWM
 Each module provides 6 output channels
 Supports independent mode for BPWM output/Capture input channel
 Supports 12-bit prescaler from 1 to 4096
 Supports 16-bit resolution BPWM counter, each module provides 1 BPWM counter
– Up, down or up/down counter operation type
 Supports mask function and tri-state enable for each BPWM pin
 Supports interrupt on the following events:
– BPWM counter match 0, period value or compared value
 Supports trigger ADC on the following events:
– BPWM counter match 0, period value or compared value
 Capture Function Features
– Up to 12 capture input channels with 16-bit resolution
– Supports rising or falling capture condition
– Supports input rising/falling capture interrupt
– Supports rising/falling capture with counter reload option

Watchdog
 20-bit free running up counter for WDT time-out interval
 Clock sources from LIRC (default), HCLK/2048 or LXT
 9 selectable time-out period from 488us ~ 32 sec
 Able to wake up from Power-down or Idle mode
 Interrupt or reset selectable on watchdog time-out
 Selectable WDT reset delay period, including 1026, 130, 18 or 3 WDT_CLK reset delay period
 Force WDT enabled after chip power on or reset.
 WDT time-out wake-up function only if WDT clock source is selected as LIRC or LXT

Window Watchdog
 Clock sources from HCLK/2048 (default) or LIRC
 Window set by 6-bit down counter with 11-bit prescaler
 WWDT counter suspends in Idle/Power-down mode
 Supports Interrupt

RTC
 Supports external power pin VBAT
 Software compensation by setting frequency compensate register (FCR),compensated clock accuracy reaches ±5ppm within 5 seconds
 RTC counter (second, minute, hour) and calendar counter (day, month, year)
 Alarm registers (second, minute, hour, day, month, year)
 Selectable 12-hour or 24-hour mode
 Automatic leap year recognition
 Day of the Week counter
 Daylight Saving Time software control
 Periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 or 1 second
 1 Hz clock output for RTC calibration
 Wake-up from idle mode and Power-down mode
 32 kHz oscillator gain control
 RTC Time Tick and Alarm Match interrupt

Analog Interfaces
EADC
 Conversion results held in up to 7 data registers with valid and overrun indicators.
 Analog input voltage: 0~VREF (Max to AVDD).
 Reference voltage from VREF pin, AVDD or internal VREF
 12-bit resolution and 10-bit accuracy guaranteed
 Up to 16 single-end analog external input channels
 Supports 3 internal channels:
– Band-gap VBG output or Internal voltage reference
– Temperature sensor input
– VBAT voltage measure (VBAT/4)
 Four ADC interrupts (ADINT0~3) with individual interrupt vector addresses.
 ADC clock frequency up to 16 MHz.
 Up to 730 KSPS conversion rate.
 Configurable ADC internal sampling time
 Up to 7 sample modules
– Each of sample module 0~3 is configurable for ADC converter
channel
– EADC_CH0~15 and trigger source.
– Configurable PDMA
– Configured resolution for 12-bit or 16-bit result
– Supports Left-adjusted result
– Averaging and oversampling (2n times, n=0~8) to support up to 16-bit result
– Sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap voltage, temperature sensor, and battery power (VBAT/4).
– Configurable sampling time for each sample module.
– Conversion results held in 19 data registers with valid and overrun indicators.
 Supports digital comparator to monitor conversion result that can be under or over the compare register setting
 Generate an interrupt when conversion result matches the compare register setting.
 Internal reference voltage source:
– 1.536V, 2.048V, 2.560V, 3.072V, or 4.096V
 An A/D conversion can be started by:
– Write 1 to SWTRGn (EADC_SWTRG[n], n = 0~18)
– External pin EADC0_ST
– Timer0~3 overflow pulse triggers
– ADINT0/1 interrupt EOC (End of conversion) pulse triggers
– BPWM triggers
 Supports PDMA transfer
 Auto turn on/off ADC power at power down or operation mode with wait state

DAC
 Up to two 12-bit 1 MSPS voltage type DAC
 Analog output voltage: 0~VREF (AVDD)
 Supports 8-bit and 12-bit mode
 Rail to rail settle time 6us
 Reference voltage selects from internal reference voltage, AVDD or VREF pin
 Max. output voltage AVDD -0.2V at buffer mode
 Conversion started by software enable, Timer interrupt flag(TIF) or PDMA trigger
 Voltage output buffer mode and bypass voltage output buffer mode
 Supports PDMA mode

Analog Comparator (ACMP)
 Up to two rail-to-rail analog comparators
 4 multiplexed I/O pins at positive node
 Negative node:
– One I/O pin
– Band-gap (VBG)
– DAC0 output
– Comparator Reference Voltage (CRV)
 Programmable propagation speed and low power consumption
 Interrupts generated when compare results change (Interrupt event condition programmable)
 Supports Power-down Wake-up
 Supports triggers for break events and cycle-by-cycle control for PWM
 Supports window compare mode and window latch mode
 Supports programmable hysteresis window:
– 0 mV, 10 mV, 20 mV or 30 mV

Internal Reference Voltage
 Internal reference voltage select: 1.536V, 2.048V, 2.560V, 3.072V, 4.096V for EADC, DAC and CRV (comparator reference voltage) reference voltage

Capactitive Touch
 Supports up to 24 touch keys.
 Supports flexible reference channel setting, at least 1 reference channel needed.
 Programmable sensitivity levels for each channel
 Programmable scanning speed for different applications.
 Supports any touch key wake-up for low-power applications.
 Supports single key-scan and programmable periodic key-scan.
 Programmable interrupt options for key-scan complete with or without threshold control.
 Supports independent reference capacitor bank (RefCB) registers for each channels
 Supports Timer0~3 time-out interrupt signal(TIF) to trigger touch key scan

Com/Seg LCD
 Supports the following COM/SEG configurations:
– Up to 352 dots (8-COM x 44-SEG)
– Up to 276 dots (6-COM x 46-SEG)
– Up to 192 dots (4-COM x 48-SEG)
 Supports maximum 8 COM driving pins, multiplexed with GPIO pins
 Supports maximum 48 SEG driving pins, multiplexed with GPIO pins
 Supports 3 bias voltage levels 1/2, 1/3, and 1/4
 Supports 8 duty ratios 1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, and 1/8
 Supports clock frequency divider from 0 to 1023 to configure the LCD operating frequency
 Configurable frame counting event interrupt period
 Supports LCD blinking display controlled by frame counting event
 Supports LCD frame end interrupt
 LCD keeps display or blinking even if in Power-down mode when LCD clock source is selected as LIRC or LXT
 Supports both type A and type B driving waveforms
 Programmable Charge Pump output voltage VLCD from 3.0V ~ 5.2V
 Selectable VLCD source from Charge Pump output or external pin
 Programmable buffer enable selection to enhance COM and SEG driving capability
 With internal resistive series network to generate reference voltage for COM and SEG voltage
 With big resistor series network to save power and small resistor series network to drive COM and SEG directly by software selection.
 LCD panel loading detect feature

Communication Interfaces
UART
 Supports up to 4 UARTs: UART0, UART1, UART2 and UART3
 UART baud rate clock from LXT(32.768 kHz) with 9600bps in Power-down mode
 Baud rate up to 10 Mbps
 Full-duplex asynchronous communications
 Supports one-wire half-duplex communications
 Separates receive and transmit 16/16 bytes FIFO
 Programmable receiver buffer trigger level
 Hardware auto-flow control (CTS and RTS)
 IrDA (SIR) function
– Supports 3/16 bit duration for normal mode
 RS-485 9-bit mode and direction control
 UART0 supports LIN function
– LIN master/slave mode
– Programmable break generation function for transmitter
– Break detection function for receiver
 Programmable baud-rate generator up to 1/16 system clock
 8-bit receiver FIFO time-out detection function
 Programmable transmitting data delay time between the last stop and the next start bit
 Auto-Baud Rate measurement and baud rate compensation function
 Break error, frame error, parity error and receive/transmit FIFO overflow detection function
 Supports RS-485 mode:
– RS-485 9-bit mode
– Hardware or software enables to program nRTS pin to control RS-485 transmission direction
– nCTS, incoming data, Received Data FIFO reached threshold and RS-485 Address Match (AAD mode) wake-up function in Power-down mode.
– Hardware or software enables to program nRTS pin to control RS-485 transmission direction
 Fully programmable serial-interface:
– Programmable number of data bit, 5-, 6-, 7-, 8- bit character
– Programmable parity bit, even, odd, no parity or stick parity bit generation and detection
– Programmable stop bit, 1, 1.5, or 2 stop bit generation
 Supports PDMA mode

Smart Card Interface
Smart card mode
 ISO 7816-3 T = 0, T = 1 compliant
 EMV2000 compliant
 One ISO 7816-3 port
 Separates receive/transmit 4 byte entry FIFO for data payloads
 Programmable transmission clock frequency
 Programmable receiver buffer trigger level
 Programmable guard time selection (11 ETU ~ 267 ETU)
 One 24-bit timer and two 8-bit timers for Answer to Request (ATR) and waiting times processing
 Supports auto direct / inverse convention function
 Supports transmitter and receiver error retry and error number limiting function
 Supports hardware activation sequence process, and the time
between PWR on and CLK start is configurable
 Supports hardware warm reset sequence process
 Supports hardware deactivation sequence process
 Supports hardware auto deactivation sequence when the card removal is detected
UART mode
 Full duplex, asynchronous communications
 Separates receiving / transmitting 4 bytes entry FIFO for data payloads
 Supports programmable baud rate generator
 Supports programmable receiver buffer trigger level
 Programmable transmitting data delay time between the last stop bit leaving the TX-FIFO and the de-assertion
 Programmable even, odd or no parity bit generation and detection
 Programmable stop bit, 1- or 2- stop bit generation

SPI
 Supports Master or Slave mode operation
 Master and slave mode up to 25 MHz (when chip works at VDD = 3.0 ~ 5.5V)
 Supports 2-bit Transfer mode
 Supports Dual and Quad I/O Transfer mode
 Configurable bit length of a transaction word from 8 to 32-bit
 Provides separate 8-level depth transmit and receive FIFO buffers
 Supports MSB first or LSB first transfer sequence
 Supports Byte Reorder function
 Supports Byte or Word Suspend mode
 Supports PDMA transfer
 Supports 3-Wire, no slave selection signal, bi-direction interface
 Supports one data channel half-duplex transfer
 Supports receive-only mode

I2C
 Up to 2 sets of I2C devices
 Master/Slave mode
 Bidirectional data transfer between masters and slaves
 Multi-master bus (no central master)
 7-bit and 10-bit addressing mode
 Standard mode (100 kbps), Fast mode (400 kbps) and Fast mode plus (1 Mbps)
 Arbitration between simultaneously transmitting masters without
corruption of serial data on the bus
 Serial clock synchronization allows devices with different bit rates to communicate via one serial bus
 Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer
 Supports 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and timer-out counter overflows
 Programmable clocks allow versatile rate control
 Multiple address recognition (four slave address with mask option)
 Supports setup/hold time programmable
 Supports SMBus and PMBus
 Multi-address Power-down wake-up function
 Supports PDMA transfer

SPI/I2S
SPI Mode
 Up to 2 sets of SPI controllers
 Master or Slave mode operation
 Configurable bit length of a transfer word from 8 to 32-bit
 Provides separate 4-level of 32-bit (or 8-level of 16-bit) transmit and receive FIFO buffers which depended on SPI setting of data width
 MSB first or LSB first transfer sequence
 Supports byte reorder function
 Byte or Word Suspend mode
 Master and slave mode up to 25 MHz (VDD = 3.0V ~5.5V)
 Supports one data channel half-duplex transfer
 Supports receive-only mode
 Supports PDMA transfer
I2S Mode
 Up to 2 sets of I2S by SPI controllers
 Interface with external audio CODEC
 Supports Master and Slave mode
 Capable of handling 8-, 16-, 24- and 32-bit word sizes
 Mono and stereo audio data
 PCM mode A, PCM mode B, I2S and MSB justified data format
 Each provides two 4-level FIFO data buffers, one for transmitting and the other for receiving
 Generates interrupt requests when buffer levels cross a programmable boundary
 Each supports two PDMA requests, one for transmitting and the other for receiving

Universal Serial Control Interface (USCI)
 Up to 2 sets of USCI
 Supports UART, SPI and I2C function
 Single byte TX and RX buffer mode
USCI_UART
 One transmit buffer and two receive buffer for data payload
 Hardware auto flow control function and programmable flow control trigger level
 Programmable baud-rate generator
 Supports 9-bit data transfer
 Baud rate detection by built-in capture event of baud rate generator
 Supports Wake-up function (Data and nCTS Wakeup Only)
 Supports PDMA transfer
USCI_SPI
 Master or Slave mode operation
 Configurable bit length of a transfer word from 4 to 16-bit
 One transmit buffer and two receive buffer for data payload
 MSB first or LSB first transfer sequence
 Word suspend function
 Supports PDMA transfer
 Supports 3-wire, no slave select signal, bi-direction interface
 Wake-up function: input slave select transition
 Supports one data channel half-duplex transfer
USCI_I2C
 Full master and slave device capability
 7-bit/10-bit addressing mode
 Communication in Standard mode (100 kbps), Fast mode (up to 400 kbps) and Fast mode plus (1 Mbps)
 Multi-master bus
 One transmit buffer and two receive buffer for data payload
 10-bit bus time out capability
 Supports Bus monitor mode
 Wake-up by data toggle or address match in Power-down mode
 Multiple address recognition
 Setup/hold time programmable

GPIO
 Four I/O modes:
– Quasi bi-direction
– Push-Pull output
– Open-Drain output
– Input only with high impendence
 TTL/Schmitt trigger input selectable
 I/O pin configured as interrupt source with edge/level trigger setting
 Independent pull-up/pull-down control
 High driver and high sink current I/O (up to 16 mA at 5V, 25°C)
 Minimum I/O Speed
– 25 MHz when VDD = 2.7 ~ 5.5 V (-40°C ~ +105°C, CL=30p, high skew rate enabled)
– 10 MHz when VDD = 1.75 ~ 5.5 V (-40°C ~ +105°C, CL=30p, high skew rate enabled)
 Software selectable slew rate control
 Supports wake-up function
 Supports I/O de-bounce with LIRC at power down
 I/O configurations of multi-function pin are controlled by module or MFOS register settings
 Supports 5V tolerance except PF2, PF3, PF4 and PF5 pins

Advanced Connectivity
USB 2.0 Full Speed
 Compliant with USB 2.0 Full-Speed specification
 Provides 1 interrupt vector with 5 different interrupt events (SOF, NEVWK, VBUSDET, USB and BUS)
 Suspend function when no bus activity exists for 3 ms
 Supports 12 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types and maximum 1024 bytes buffer size
 Provides remote wake-up capability
 Start of Frame (SOF) locked clock pulse generation
 Supports USB 2.0 Link Power Management (LPM)
 Supports Crystal-less function
 Supports Battery charging 1.2 (BC1.2)