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ALC3261-CG Arkusz danych (PDF) - Realtek Semiconductor Corp.

ALC3261-CG Datasheet PDF - Realtek Semiconductor Corp.
Numer części ALC3261-CG
Pobierz  ALC3261-CG Pobierz

Rozmiar pliku   1244.24 Kbytes
Page   130 Pages
Producent  REALTEK [Realtek Semiconductor Corp.]
Strona internetowa  https://www.realtek.com/en/
Logo REALTEK - Realtek Semiconductor Corp.
Szczegółowy opis FOUR CHANNEL I2S/PCM AUDIO CODEC WITH VOICE DSP

ALC3261-CG Datasheet (PDF)

Go To PDF Page Pobierz Arkusz danych
ALC3261-CG Datasheet PDF - Realtek Semiconductor Corp.

Numer części ALC3261-CG
Pobierz  ALC3261-CG Click to download

Rozmiar pliku   1244.24 Kbytes
Page   130 Pages
Producent  REALTEK [Realtek Semiconductor Corp.]
Strona internetowa  https://www.realtek.com/en/
Logo REALTEK - Realtek Semiconductor Corp.
Szczegółowy opis FOUR CHANNEL I2S/PCM AUDIO CODEC WITH VOICE DSP

ALC3261-CG Arkusz danych (HTML) - Realtek Semiconductor Corp.

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ALC3261-CG Szczegóły Produktu

Description
The ALC3261 is a low power, dual I2S interface, 4 channels DAC and 2 channel ADC Audio Codec with
a optimized Voice DSP integrated. The primary I2S interface connects to system host chip and its
secondary I2S interface can perform as input or output device connected to external processor, blue tooth
device or wireless transceiver.
ALC3261 is a highly integration of audio subsystem chip, including two stereo DACs with 100dB SNR,
one stereo ADC with 94dB SNR, stereo Class-D speaker amplifiers provides 1.5W per channel into 8Ω or
2.5W per channel into 4Ω with a 5V supply with excellent PSRR and low EMI, a mono differential
earpiece amplifier is also provided, providing output from any DAC or Analog-in.
The ALC3261 features an extra low power cap-free headphone amplifier. It consumes only less than
10mW power during playback, providing tablet system longer battery life under headphone listening
mode.
The integrated DRC (Dynamic Range Controller) and parametric Equalizer provides further digital sound
processing capability of audio playback paths. The DRC in ALC3261 continuously monitors the DAC
output level. When the power level is low, it increases the input signal gain to make it sound louder. At
the same time, if a peaking signal is detected, it autonomously reduces the applied gain to avoid hard
clipping. It ensures the maximum/consistent signal amplitude without producing audio clipping and
speaker damage. The parametric Equalizer contains 7 independent filters with programmable gain, center
frequency and bandwidth to tailor the frequency characteristics of embedded speaker system according to
user preferences.
ALC3261 embedded a low power wideband voice DSP. This optimized voice DSP provides excellent
noise suppression, echo cancellation and beam forming performance. It combines 8 kHz and 16 kHz
sampling rate and 75MIPS digital signal processing capability to achieve high fidelity and non-stationary
wideband performance.

Features
Two Stereo Digital-to-Analog Converters with 100dBA SNR
One Stereo Analog-to-Digital Converter with 94dBA SNR
Differential analog microphone inputs with boost pre-amplifiers and low noise microphone bias
 +20/+24/+30/+35/+40/+44/+50/+52 dB microphone boost gain
 MIC input to ADC with 50dB boost gain, SNR > 66dBA and THD+N < -65dB
 Adjustable microphone reference voltage (0.9*MICVDD or 0.75*MICVDD)
Stereo line level input
 Line level input to ADC with 0dB gain, SNR >= 94dBA, THD+N <= -83dB
Stereo line level output
 ADC to line level output with 0dB gain, SNR >= 100dBA, THD+N <= -86dB
Stereo/Mono BTL (Bridge-Tied-Load) Class-D amplifier
 650mW/CH (SPKVDD=3.6V, THD+N < = 1%, 8 Load)
 500mW/CH (SPKVDD=3.6V, THD+N < = 0.1%, 8 Load)
 1.2W/CH (SPKVDD=5.0V, THD+N < = 1%, 8 Load)
 2.5W/CH (SPKVDD=5.0V, THD+N < = 10%, 4 Load)
 2.1W/CH (SPKVDD=5.0V, THD+N < = 1%, 4 Load)
 Auto speaker ratio gain for SPKVDD = 3.3V ~ 5.0V
Stereo Cap-Free headphone amplifier with extra low power consumption for playback
 20mW/CH (AVDD=CPVDD=1.8V, THD+N <= -80dB, 16 Load)
 Playback power consumption <= 10mW (AVDD=VBVDD=CPVDD=1.8V, 16, With I2S
Clock, Playback Silence)
 Playback power consumption <= 13mW (AVDD=VBVDD=CPVDD=1.8V, 16, With I2S
Clock, Playback 1mW/channel to 32 headphone)
Mono differential receiver amplifier
 50mW/CH (AVDD=CPVDD=1.8V, THD+N <= -70dB, 16 Load, BTL mode)
Audio jack insert detection
Inside PLL can receiver wide range clock input
Two 24bit/8kHz ~ 192kHz I2S/PCM interface for each mono DAC and stereo DAC
Two 24bit/8kHz ~ 192kHz I2S/PCM interface for stereo ADC
I2C control interface
Two digital microphone interfaces supported
Asynchronous sample rate converter (ASRC) for each interface
Programmable register table with two sequencers
7-bands parametric equalizer (EQ) for DAC path or ADC path
Enhanced DRC(Dynamic Range Control)/AGC(Auto Gain Control) with compression function for
DAC path or ADC path
Zero detection and soft volume for pop noise suppression
Speaker amplifier DC term self-test function for speaker protection
Voice Processing
 Noise Reduction
 Beam Forming with Stereo Microphone
 Far Field Pick-Up Technology

Application
Smart Phones
Tablet




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