AM652X datasheet(276/299 Pages) TI1

276 / 299 page

276

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Detailed Description

•

PCIe Advanced Error Reporting

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PCIe messages for both transmit and receive

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Filtering for Posted, Non-posted, and Completion traffic

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Configurable BAR filtering, I/O filtering, configuration filtering, and completion lookup/timeout

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Access to configuration space registers and external application memory-mapped registers through

BAR0 and through configuration access

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Legacy interrupts reception (in RC mode) and generation (in EP mode)

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MSI-X generation and reception

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Precision Time Measurement in combination with time-stamp (CPTS) module

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Quality-of-Service (QoS) mechanism by enabling priority or round-robin arbitration on VCs

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Two host bus master interfaces for high and low priority traffic mapped to four virtual channels

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PCIe compliant PHY (PIPE 4.0) interface for connection to a SERDES based PHY

The PCIe subsystems do not support the following features:

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PCIe beacon for in-band wake

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Vendor Messaging

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I/O access in inbound direction in RC or EP mode

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Single-root I/O Virtualization (SR-IOV)

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Address Translation Services (ATS)

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Addressing modes other than incremental for burst transactions. As a result, the PCIe addresses

cannot be in cacheable memory space.

For more information, see section Peripheral Component Interconnect Express (PCIe) Subsystem in

chapter Peripherals of the device TRM.

6.11.23 SerDes

SerDes goal is to convert device (SoC) parallel data into serialized data that can be output over a high-

speed electrical interface. In the opposite direction, SerDes converts high-speed serial data into parallel

data that can be processed by the device. To this end, the SerDes contains a variety of functional blocks

to handle both the external analog interface as well as the internal digital logic.

The device contains two SerDeses.

Most important building blocks of SerDes are:

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Lanes: The lanes handle all inputs and outputs from the serial interface, and contain the Tx/Rx I/Os,

serializer/deserializer, and Clock and Data Recovery (CDR) unit.

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Clock Multiplier Unit (CMU): The CMU handles peripheral and Tx clocking of the SerDes. It consists of

an internal PLL and the reference clock input buffers.

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Physical Coding Sub-block (PCS): The PCS is responsible for translating data from/to the parallel

interface, as well as data encoding/decoding and symbol alignment.

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WIZ: The WIZ acts as a wrapper for the SerDes, and can both send control signals to and report status

signals from the SerDes, and muxes SerDes to peripherals.

The SERDES PHY module features include:

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Single lane PHY containing:

–

Transmit and Receive I/Os

–

Serializer

–

Deserializer

–

Clock and data recovery (CDR) unit

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