AM79C930VCW datasheet(111/161 Pages) AMD

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Am79C930

Delimiter may be used for start of frame recognition by appropriate

settings of the SD[1:0] bits in the Network Configuration Register

(TCR0).

Start of Frame detection is performed on the bits in the or-

der that they appear on the medium, with the SDLT LSB, bit 0, being

checked against the first bit to arrive at the Am79C930 (RX case) or

the first bit to leave the Am79C930 (Tx case) and continuing in

that order.

TCR11: Interrupt Register 3

This register is the TAI Interrupt Register 3. Provides in-

terrupt status information. Any interrupt bit may be

cleared by writing a 1 to the bit location. Writing a 0 to a

bit location has no effect on the bit value. An interrupt in

TCR11 will be signaled in TIR4 through the MOREINT

bit when the associated unmask bit has been set in

TCR12.

CONFIGURATION REGISTER INDEX:

0Bh

Bit

Name

Reset Value

Description

7:4

Reserved

–

Reserved. Must be written as a 0. Reads of these bits produce

undefined data.

U1INT

USER1 Interrupt. When U1INT is set to 1, it indicates that a change

of state has occurred at the USER1/IRQ12 pin. The change of state

required to signal an interrupt on the U1INT bit is determined by the

settings of the U1INTSC bits of TCR7[4:3]. This function may be

disabled with an appropriate setting of the U1INTSC bits. A corre-

sponding unmask bit for this interrupt source exists in TCR12.

RUNERR

Run Length Error. When RUNERR is set to a 1, it indicates that the

total number of 1s during a received message exceeds the total

number of 0s at any given time by 25, or that the total number of 0s

in the message at any given time exceeds the number of 1s in the

message by 27. This function may be disabled with the DISRNR bit

of TCR27.

ATFO

Asynchronous Transmit FIFO Overflow. When ATFO is set to 1, it

indicates that the asynchronous transmit FIFO has overflowed.

ATFU

Asynchronous Transmit FIFO Underflow. When ATFU is set to 1, it

indicates that the asynchronous transmit FIFO has underflowed.

TCR12: Interrupt Unmask Register 3

This register is the Interrupt Unmask Register 3.

Each bit in this register will unmask the corresponding

interrupt of the Interrupt Register 2 (TIR5) when the un-

mask bit is set to 1.

CONFIGURATION REGISTER INDEX:

0Ch

Bit

Name

Reset Value

Description

7:4

Reserved

–

Reserved. Must be written as a 0. Reads of these bits produce

undefined data.

U1INTU

USER1 Interrupt Unmask.

RUNERRU

RUNERR Interrupt Unmask.

ATFOU

Asynchronous Transmit FIFO Overflow Interrupt Unmask.

ATFUU

Asynchronous Transmit FIFO Underflow Interrupt Unmask.

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