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SH7041A Arkusz danych(PDF) 434 Page - Renesas Technology Corp |
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SH7041A Arkusz danych(HTML) 434 Page - Renesas Technology Corp |
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434 / 923 page ![]() 396 12.7.8 Contention between Buffer Register Write and Input Capture If an input capture signal is issued in the T 2 state of the buffer write cycle, write to the buffer register does not occur, and buffer operation takes priority (figure 12.83). TGR Input capture signal TCNT Address Write signal Buffer register φ T1 T2 Buffer register write cycle Buffer register address N MN M Figure 12.83 Buffer Register Write and Input Capture Contention |
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