HC705JJ7GRSSLASHD datasheet(101/230 Pages) NXP

Numer części	HC705JJ7GRS/D

Szczegółowy opis	Low-Cost, HC05 Core MCU in 20-Pin Package (MC68HC705JJ7) or 28-Pin Package (MC68HC705JP7)

PDF	230 Pages

Scroll/Zoom	100%

Producent	NXP [NXP Semiconductors]

Strona internetowa	http://www.nxp.com

Logo

101 / 230 page

Parallel Input/Output

Port C (28-Pin Versions Only)

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Parallel Input/Output

7.5.4 Port C Logic

Figure 7-15 shows the I/O logic of port C.

When a port C pin is programmed as an output, reading the port bit

actually reads the value of the data latch and not the voltage on the pin

itself. When a port C pin is programmed as an input, reading the port bit

reads the voltage level on the pin. The data latch can always be written,

regardless of the state of its DDR bit. Table 7-4 summarizes the

operations of the port C pins.

Figure 7-15. Port C I/O Circuit

PCx

PORT C DATA

BIT PCx

READ $0006

WRITE $0002

READ $0002

WRITE $0010

PULLDOWN

DEVICE

RESET

WRITE $0006

DATA DIRECTION

BIT DDRCx

PULLDOWN

BIT PDICx

MASK OPTION REGISTER ($1FF1)

HIGH SINK/SOURCE

CURRENT CAPABILITY

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JJ7GRS/D Arkusz danych(PDF) 101 Page - NXP Semiconductors