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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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PQFP100 Arkusz danych(PDF) 195 Page - STMicroelectronics |
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PQFP100 Arkusz danych(HTML) 195 Page - STMicroelectronics |
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195 / 429 page  195/429 MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) 10.4.3.9 TxINA = Clock Up - TxINB = Clock Down The edge received on input pin A (or B) performs a one step up (or down) count, so that the counter clock and the up/down control are external. Setting the UDC bit in the TCR register has no effect in this configuration, and input pin B has priority on input pin A. 10.4.3.10 TxINA = Up/Down - TxINB = Ext Clock An High (or Low) level applied to input pin A sets the counter in the up (or down) count mode, while the signal applied to input pin B is used as clock for the prescaler. Setting the UDC bit in the TCR reg- ister has no effect in this configuration. 10.4.3.11 TxINA = Trigger Up - TxINB = Trigger Down Up/down control is performed through both input pins A and B. A edge on input pin A sets the up count mode, while a edge on input pin B (which has priority on input pin A) sets the down count mode. The counter clock is internally generated, and setting the UDC bit in the TCR register has no effect in this configuration. 10.4.3.12 TxINA = Up/Down - TxINB = I/O An High (or Low) level of the signal applied on in- put pin A sets the counter in the up (or down) count mode. The counter clock is internally generated. Setting the UDC bit in the TCR register has no ef- fect in this configuration. 9 |
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