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ST10F276 Arkusz danych(PDF) 205 Page - STMicroelectronics |
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ST10F276 Arkusz danych(HTML) 205 Page - STMicroelectronics |
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205 / 229 page  ST10F276 Electrical characteristics 205/229 23.8.17 External memory bus timing In the next sections the External Memory Bus timings are described. The given values are computed for a maximum CPU clock of 40 MHz. It is evident that when higher CPU clock frequency is used (up to 64 MHz), some numbers in the timing formulas become zero or negative, which in most cases is not acceptable or meaningful. In these cases, the speed of the bus settings tA, tC and tF must be correctly adjusted. Note: All External Memory Bus Timings and SSC Timings presented in the following tables are given by design characterization and not fully tested in production. |
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