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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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PIC18F44J10-E/ML Arkusz danych(PDF) 139 Page - Microchip Technology |
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PIC18F44J10-E/ML Arkusz danych(HTML) 139 Page - Microchip Technology |
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139 / 358 page  © 2007 Microchip Technology Inc. Preliminary DS39682C-page 137 PIC18F45J10 FAMILY 14.4.5 FULL-BRIDGE MODE In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin P1A is continuously active and pin P1D is modulated. In the Reverse mode, pin P1C is continuously active and pin P1B is modulated. These are illustrated in Figure 14-6. P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2> and PORTD<7:5> data latches. The TRISC<2> and TRISD<7:5> bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs. FIGURE 14-6: FULL-BRIDGE PWM OUTPUT Period Duty Cycle P1A(2) P1B(2) P1C(2) P1D(2) Forward Mode (1) Period Duty Cycle P1A(2) P1C(2) P1D(2) P1B(2) Reverse Mode (1) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. |
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