PM7366-PI datasheet(153/286 Pages) PMC

153 / 286 page

RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

140

Bit

Type

Function

Default

Bit 31 to

Bit 16

Unused

XXXXH

Bit 15

R/W

RQB[31]

Bit 14

R/W

RQB[30]

Bit 13

R/W

RQB[29]

Bit 12

R/W

RQB[28]

Bit 11

R/W

RQB[27]

Bit 10

R/W

RQB[26]

Bit 9

R/W

RQB[25]

Bit 8

R/W

RQB[24]

Bit 7

R/W

RQB[23]

Bit 6

R/W

RQB[22]

Bit 5

R/W

RQB[21]

Bit 4

R/W

RQB[20]

Bit 3

R/W

RQB[19]

Bit 2

R/W

RQB[18]

Bit 1

R/W

RQB[17]

Bit 0

R/W

RQB[16]

This register provides the more significant word of the Receive Queue Base address. The

contents of the companion RMAC Receive Queue Base LSW register is held in a holding register

until a write access to this register, at which point, the base address of the receive queue is

updated.

Note

This register is not byte addressable. Writing to this register modifies all the bits in the register.

Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all

four byte enables are negated, no access is made to this register.

RQB[31:0]:

The receive queue base bits (RQB[31:0]) provides the base address of the Large Buffer

RPDR Free, Small Buffer RPDR Free and RPDR Ready queues in PCI host memory. This

PM7366-PI Arkusz danych(PDF) 153 Page - PMC-Sierra, Inc

PM7366-PI Arkusz danych(HTML) 153 Page - PMC-Sierra, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Arkusz danych Pobierz

Link URL