ST7LITE0XY0 datasheet(105/124 Pages) STMICROELECTRONICS

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ST7LITE0xY0, ST7LITESxY0

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ADC CHARACTERISTICS (Cont’d)

Figure 82. RAIN max. vs fADC with CAIN=0pF

Figure 83. Recommended CAIN/RAIN values

Notes:

1. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-

pacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced.

2. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization and to allow

the use of a larger serial resistor (RAIN). It is valid for all fADC frequencies ≤ 4MHz.

13.11.1 General PCB Design Guidelines

To obtain best results, some general design and

layout rules should be followed when designing

the application PCB to shield the noise-sensitive,

analog physical interface from noise-generating

CMOS logic signals.

Properly place components and route the signal

traces on the PCB to shield the analog inputs. An-

alog signals paths should run over the analog

ground plane and be as short as possible. Isolate

analog signals from digital signals that may switch

while the analog inputs are being sampled by the

A/D converter. Do not toggle digital outputs on the

same I/O port as the A/D input being converted.

010

CPARASITIC (pF)

4 MHz

2 MHz

1 MHz

0.1

100

1000

0.01

0.1

fAIN(KHz)

Cain 10 nF

Cain 22 nF

Cain 47 nF

ST7LITE0XY0 Arkusz danych(PDF) 105 Page - STMicroelectronics