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STM32F412RET6 Arkusz danych(PDF) 116 Page - STMicroelectronics |
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STM32F412RET6 Arkusz danych(HTML) 116 Page - STMicroelectronics |
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116 / 201 page ![]() Electrical characteristics STM32F412xE/G 116/201 DocID028087 Rev 7 Figure 33 and Figure 34 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. Figure 33. PLL output clock waveforms in center spread mode Figure 34. PLL output clock waveforms in down spread mode |
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