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STM32F429NET7TR Arkusz danych(PDF) 114 Page - STMicroelectronics |
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STM32F429NET7TR Arkusz danych(HTML) 114 Page - STMicroelectronics |
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114 / 231 page ![]() Electrical characteristics STM32F427xx STM32F429xx 114/231 DocID024030 Rev 6 APB2 (up to 90 MHz) SDIO 8.11 8.75 7.83 µA/MHz TIM1 17.11 15.97 14.17 TIM8 17.33 16.11 14.33 TIM9 7.22 6.67 6.00 TIM10 4.56 4.31 3.83 TIM11 4.78 4.44 4.00 ADC1(5) 4.67 4.31 3.83 ADC2(5) 4.78 4.44 4.00 ADC3(5) 4.56 4.17 3.67 SPI1 1.44 1.39 1.17 USART1 4.00 3.75 3.33 USART6 4.00 3.75 3.33 SPI4 1.44 1.39 1.17 SPI5 1.44 1.39 1.17 SPI6 1.44 1.39 1.17 SYSCFG 0.78 0.69 0.67 LCD_TFT 39.89 37.22 33.17 SAI1 3.78 3.47 3.17 1. When the I/O compensation cell is ON, IDD typical value increases by 0.22 mA. 2. The BusMatrix is automatically active when at least one master is ON. 3. To enable an I2S peripheral, first set the I2SMOD bit and then the I2SE bit in the SPI_I2SCFGR register. 4. When the DAC is ON and EN1/2 bits are set in DAC_CR register, add an additional power consumption of 0.8 mA per DAC channel for the analog part. 5. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part. Table 35. Peripheral current consumption (continued) Peripheral IDD( Typ)(1) Unit Scale 1 Scale 2 Scale 3 |
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