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STM32F429NET7 Arkusz danych(PDF) 189 Page - STMicroelectronics |
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STM32F429NET7 Arkusz danych(HTML) 189 Page - STMicroelectronics |
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189 / 231 page  DocID024030 Rev 6 189/231 STM32F427xx STM32F429xx Electrical characteristics 192 6.3.28 LCD-TFT controller (LTDC) characteristics Unless otherwise specified, the parameters given in Table 107 for LCD-TFT are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 17, with the following configuration: • LCD_CLK polarity: high • LCD_DE polarity : low • LCD_VSYNC and LCD_HSYNC polarity: high • Pixel formats: 24 bits Table 107. LTDC characteristics Symbol ParameterMin Max Unit fCLK LTDC clock output frequency - 42 MHz DCLK LTDC clock output duty cycle 45 55 % tw(CLKH) tw(CLKL) Clock High time, low time tw(CLK)/2 − 0.5 tw(CLK)/2+0.5 ns tv(DATA) Data output valid time - 3.5 th(DATA) Data output hold time 1.5 - tv(HSYNC) HSYNC/VSYNC/DE output valid time -2.5 tv(VSYNC) tv(DE) th(HSYNC) HSYNC/VSYNC/DE output hold time 2- th(VSYNC) th(DE) |
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