IS25LE01G-RILA3-TY datasheet(172/186 Pages) ISSI

Numer części	IS25LE01G-RILA3-TY

Szczegółowy opis	SERIAL FLASH MEMORY 133/104MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC

PDF	186 Pages

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Producent	ISSI [Integrated Silicon Solution, Inc]

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172 / 186 page

IS25LE01G

IS25WE01G

Integrated Silicon Solution, Inc.- www.issi.com

172

Rev. A6

01/14/2025

8.69 WRITE ECC REGISTER OPERATION (WRECC, B5h)

Before the Write ECC Register (WRECC) command can be accepted by the device, a Write Enable (WREN)

command must be issued and decoded by the device. After the Write Enable (WREN) command has been

decoded successfully, the device will set the Write Enable Latch (WEL) to enable the WRECC operation.

The WRECC command (B5h) is entered by shifting the instruction and data byte on SI.

CE# must be driven to the logic high state after the eighth (8th) bit of data has been latched. If not, the WRECC

command is not executed. As soon as CE# is driven to the logic high state, the WRECC operation is initiated with

no delays.

Figure 8.150 WRECC Sequence In SPI Mode

Instruction = B5h

CE #

SCK

Data In

Mode 3

Mode 0

High Impedence

Figure 8.151 WRECC Sequence In QPI Mode

B5h

Mode 3

Mode 0

7:4

3:0

CE#

SCK

IO[3:0]

Data In

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