GD32H757ZMT7 datasheet(109/151 Pages) GIGADEVICE

109 / 151 page

GD32H757xx Datasheet

108

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

1.8 V ≤ VDDA ≤ 2.4 V

1.8 V ≤ VREFP ≤ VDDA

fADC =

36 MHz

SMP

= 3.5

—

2.25

Resolution =

10 bits

2.7 V ≤ VDDA ≤ 3.6 V

2.7 V ≤ VREFP ≤ VDDA

fADC =

72 MHz

SMP

= 3.5

—

5.14

2.4 V ≤ VDDA ≤ 2.7 V

2.4 V ≤ VREFP ≤ VDDA

fADC =

54 MHz

SMP

= 3.5

—

3.85

1.8 V ≤ VDDA ≤ 2.4 V

1.8 V ≤ VREFP ≤ VDDA

fADC =

36 MHz

SMP

= 3.5

—

2.57

Resolution =

8 bits

2.7 V ≤ VDDA ≤ 3.6 V

2.7 V ≤ VREFP ≤ VDDA

fADC =

72 MHz

SMP

= 3.5

—

2.4 V ≤ VDDA ≤ 2.7 V

2.4 V ≤ VREFP ≤ VDDA

fADC =

54 MHz

SMP

= 3.5

—

4.5

1.8 V ≤ VDDA ≤ 2.4 V

1.8 V ≤ VREFP ≤ VDDA

fADC =

36 MHz

SMP

= 3.5

—

tTRIG(1)

External trigger

period

Resolution = 14 bits

—

1/ fADC

VAIN(1)

Conversion

voltage range

—

VREFP

VCMIV(1)

Common mode

input voltage

—

VREFP/

10%

VREFP/

2+10

RAIN(1)

External input

impedance

Resolution = 14 bits

—

84.4

Resolution = 12 bits

—

96.5

Resolution = 10 bits

—

112

Resolution = 8 bits

—

135

RADC(1)

Internal

resistance

—

150

—

CADC(1)

Input sampling

capacitance

—

tSTAB

ADC Power-up

time

—

μs

tCAL(1)

Offset and

linearity

calibration time

—

TBD

1/fADC

tOFF_ CAL(1)

Offset calibration

time

—

TBD

1/fADC

ts(1)

Sampling time

—

3.5

—

810.5

1/fADC

tCONV(1)

Total conversion

time (including

sampling time)

Resolution = N bits

N+4

—

1/fADC

(1)

Value guaranteed by design, not 100% tested in production.

(2)

Depending on the package, VREFP can be internally connected to VDDA and VREFN to VSSA.

(3)

VREFP should always be equal to or less than VDDA, especially during power up.

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