R7KA8M2AFDCAM datasheet(190/295 Pages) RENESAS

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Table 2.69

IIC timing (1)-3

Setting of the I3C_SCL0, I3C_SDA0 pins are not required with the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

VCC

Min

Max

Unit

IIC

(Fast-mode +)

BFCTL.FMPE = 1

SCL input cycle time

tSCL

2.70 V or above,

1.65 to 1.95 V

10 (18) × tI3Ccyc + 240

—

SCL input high pulse

width

tSCLH

2.70 V or above,

1.65 to 1.95 V

5 (9) × tI3Ccyc + 120

—

SCL input low pulse width tSCLL

2.70 V or above,

1.65 to 1.95 V

5 (9) × tI3Ccyc + 120

—

SCL, SDA rise time

tSr

2.70 V or above,

1.65 to 1.95 V

—

120

SCL, SDA fall time

tSf

2.70 V or above,

1.65 to 1.95 V

20 × (external pull-up

voltage/3.3V)

120

SCL, SDA input spike

pulse removal time

tSP

2.70 V or above,

1.65 to 1.95 V

1 (4) × tI3Ccyc

SDA input bus free time

when wakeup function is

disabled

tBUF

2.70 V or above,

1.65 to 1.95 V

5 (9) × tI3Ccyc + 120

—

SDA input bus free time

when wakeup function is

enabled

5(9) × tI3Ccyc + 4 × tTcyc +

120

START condition input

hold time when wakeup

function is disabled

tSTAH

2.70 V or above,

1.65 to 1.95 V

tI3Ccyc + 120

—

START condition input

hold time when wakeup

function is enabled

1(5) × tI3Ccyc + tTcyc + 120

Restart condition input

setup time

tSTAS

2.70 V or above,

1.65 to 1.95 V

120

—

Stop condition input setup

time

tSTOS

2.70 V or above,

1.65 to 1.95 V

120

—

Data input setup time

tSDAS

2.70 V or above,

1.65 to 1.95 V

tI3Ccyc + 30

—

Data input hold time

tSDAH

2.70 V or above,

1.65 to 1.95 V

—

SCL, SDA capacitive load Cb*1

2.70 V or above,

1.65 to 1.95 V

—

550

Note:

tI3Ccyc: I3C internal reference clock (I3Cφ) cycle, tTcyc: TCLK cycle.

Note:

Values in parentheses apply when INCTL.DNFS[3:0] is set to 0011b while the digital filter is enabled with INCTL.DNFE set to 1.

Note 1. Cb indicates the total capacity of the bus line.

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 190 of 295

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