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2.3.15

SD/MMC Host Interface Timing

Table 2.75

SD/MMC Host Interface signal timing

Conditions:

High-speed high drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins:

SD0CLK_A, SD0CLK_B, SD0CLK_C, SD1CLK_A, SD1CLK_B

For other pins, high drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Clock duty ratio is 50%.

Parameter

Symbol

VCC/VCC2

Min

Max

Unit

Test conditions

SDCLK clock cycle

tSDCYC

2.70 V or above

—

Figure 2.107

1.70 to1.95 V*1

—

1.70 to1.95 V

—

SDCLK clock high pulse

width

tSDWH

2.70 V or above

6.5

—

1.70 to1.95 V*1

6.5

—

1.70 to1.95 V

13.0

—

SDCLK clock low pulse

width

tSDWL

2.70 V or above

6.5

—

1.70 to1.95 V*1

6.5

—

1.70 to1.95 V

13.0

—

SDCLK clock rise time

tSDLH

2.70 V or above

—

1.70 to1.95 V*1

—

1.70 to1.95 V

—

SDCLK clock fall time

tSDHL

2.70 V or above

—

1.70 to1.95 V*1

—

1.70 to1.95 V

—

SDCMD/SDDAT output

data delay

tSDODLY

2.70 V or above

–7.0

4.0

1.70 to1.95 V*1

–7.0

7.0

1.70 to1.95 V

–15.0

15.0

SDCMD/SDDAT input

data setup

tSDIS

2.70 V or above

4.5

—

1.70 to1.95 V*1

4.5

—

1.70 to1.95 V

20.0

—

SDCMD/SDDAT input

data hold

tSDIH

2.70 V or above

1.5

—

1.70 to1.95 V

1.5

—

Note:

Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the SD/MMC

Host interface, the AC portion of the electrical characteristics is measured for each group.

Note:

If SD1DAT4_A to SD1DAT7_A are used, characteristics above is guaranteed only when VCC = VCC2.

Note 1. Only supported for Ch0 group B ("SD0*_B") and Ch1 group A ("SD1*_A")

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

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