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ST20-GP1 Arkusz danych(PDF) 109 Page - STMicroelectronics |
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ST20-GP1 Arkusz danych(HTML) 109 Page - STMicroelectronics |
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109 / 116 page  ST20-GP1 109/116 ® 19.5.3 Direct DMA protocol In this mode PlinknotAck is active high. The initial (inactive) state of the pin is low. Figure 19.8 Byte-wide parallel port timings when using the Direct DMA protocol Symbol Parameter 16.4 Mhz 32.7 Mhz Units Min Max Min Max PLink is output tPALDOX PlinkData hold after PlinknotAck falling edge 330 160 ns tDOVPAL PlinkData valid to PlinknotAck fall- ing transition 100 40 ns PLink is input tPALDIX PlinkData hold after PlinknotAck falling edge 00 ns tDIVPAL PlinkData valid to PlinknotAck fall- ing transition 100 70 ns PLink is input or output tPAHPAL PlinknotAck high time 220 270 100 140 ns tPALPAH PlinknotAck low time 220 270 100 140 ns Table 19.7 Timings for Direct mode (Output) (Input) PlinknotAck PlinkData0-7 tDOVPAL tPAHPAL tPALDIX PlinkData0-7 tPALPAH tPALDOX tDIVPAL |
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