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ST72521 Arkusz danych(PDF) 120 Page - STMicroelectronics |
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ST72521 Arkusz danych(HTML) 120 Page - STMicroelectronics |
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120 / 211 page  ST72521 120/211 I2C BUS INTERFACE (Cont’d) 10.7.5 Low Power Modes 10.7.6 Interrupts Figure 66. Event Flags and Interrupt Generation Note: The I2C interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC reg- ister is reset (RIM instruction). Mode Description WAIT No effect on I2C interface. I2C interrupts cause the device to exit from WAIT mode. HALT I2C registers are frozen. In HALT mode, the I2C interface is inactive and does not acknowledge data on the bus. The I2C interface resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt 10-bit Address Sent Event (Master mode) ADD10 ITE Yes No End of Byte Transfer Event BTF Yes No Address Matched Event (Slave mode) ADSEL Yes No Start Bit Generation Event (Master mode) SB Yes No Acknowledge Failure Event AF Yes No Stop Detection Event (Slave mode) STOPF Yes No Arbitration Lost Event (Multimaster configuration) ARLO Yes No Bus Error Event BERR Yes No BTF ADSL SB AF STOPF ARLO BERR EVF INTERRUPT ITE * * EVF can also be set by EV6 or an error from the SR2 register. ADD10 |
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