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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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ORSPI4 Arkusz danych(PDF) 129 Page - Lattice Semiconductor |
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ORSPI4 Arkusz danych(HTML) 129 Page - Lattice Semiconductor |
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129 / 263 page  Lattice Semiconductor ORCA ORSPI4 Data Sheet 129 Clocking Schemes and Timing Diagrams- SERDES Figure 67 shows a timing diagram for the transmit section of the SERDES interface. Setup and Hold numbers at the interface are also show. Similar timing diagrams are also shown for the receive SERDES interface section in both channel alignment mode (Figure 68), and channel bypass mode (Figure 69). SERDES Align Mode Interface Figure 67. Data: TBIT9[A:D][3:0], TCOMMA[A:D][3:0], TWD[A:D][31:0] Clock: TSYS_CLK[A:D] Q 3.5/0.5 ns 1.5/0.5 ns D 2.5 / 1.3 ns FPGA Embedded Core C 1.1/ 0.18 ns D Delay ÷ 4 SERDES_CLK 311 MHZ 78 MHz TCK78 3.0ns Setup = 1.5 ns Hold = - 0.8 ns Delay NOTE: Delays represent average max/min values, not absolute values Actual delay values are used by ispLEVER Clock Buffer Delay Relative to Data FPGA Clock Tree |
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