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HD64F2149YV Arkusz danych(PDF) 209 Page - Renesas Technology Corp |
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HD64F2149YV Arkusz danych(HTML) 209 Page - Renesas Technology Corp |
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209 / 1075 page ![]() Section 7 Data Transfer Controller Rev. 3.00 Jan 18, 2006 page 181 of 1044 REJ09B0280-0300 On-chip supporting module IRQ interrupt DTVECR Interrupt controller CPU DTC DTCER Clear control Select Interrupt request Source flag cleared Clear Clear request Interrupt mask Figure 7.3 Block Diagram of DTC Activation Source Control When an interrupt has been designated a DTC activation source, existing CPU mask level and interrupt controller priorities have no effect. If there is more than one activation source at the same time, the DTC is activated in accordance with the default priorities. |
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