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H8SX/1663 Arkusz danych(PDF) 877 Page - Renesas Technology Corp |
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H8SX/1663 Arkusz danych(HTML) 877 Page - Renesas Technology Corp |
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877 / 1158 page ![]() Section 17 I 2C Bus Interface 2 (IIC2) Rev.1.00 Jun. 07, 2006 Page 825 of 1102 REJ09B0294-0100 Bit Bit Name Initial Value R/W Description 2 1 0 BC2 BC1 BC0 0 0 0 R/W R/W R/W Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. The settings of these bits should be made during intervals between transfer frames. When setting these bits to a value other than 000, the setting should be made while the SCL line is low. The value return to 000 at the end of a data transfer including the acknowledge bit. 000: 9 001: 2 010: 3 011: 4 100: 5 101: 6 110: 7 111: 8 I 2C control module can be reset without setting the ports and initializing the registers. 17.3.4 I 2C Bus Interrupt Enable Register (ICIER) ICIER enables or disables interrupt sources and the acknowledge bits, sets the acknowledge bits to be transferred, and confirms the acknowledge bit to be received. Bit Bit Name Initial Value R/W 7 TIE 0 R/W 6 TEIE 0 R/W 5 RIE 0 R/W 4 NAKIE 0 R/W 3 STIE 0 R/W 2 ACKE 0 R/W 1 ACKBR 0 R 0 ACKBT 0 R/W |
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