R8CSLASH15 datasheet(166/277 Pages) RENESAS

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R8C/14 Group, R8C/15 Group

15. Clock Synchronous Serial I/O with Chip Select (SSU)

Rev.2.10

Jan 19, 2006

Page 154 of 253

REJ09B0164-0210

15.5

Clock Synchronous Communication Mode

15.5.1

Initialization in Clock Synchronous Communication Mode

Figure 15.11 shows an Initialization in Clock Synchronous Communication Mode. Set the TE bit in the

SSER register to “0” (disables transmit) and the RE bit to “0” (disables receive) before data transmit /

receive as an initialization.

When communication mode and format are changed, set the TE bit to “0” and the RE bit to “0” before

changing.

Setting the RE bit to “0” does not change the contents of the RDRF and ORER flags, and the contents

of the SSRDR register.

Figure 15.11

Initialization in Clock Synchronous Communication Mode

Start

SSMR2 register

SSUMS bit

← 0

SSCRH register

Set CKS0 to CKS2 bits

Set RSSTP bit

SSSR register

ORER bit

← 0(1)

SSER register

RE bit

← 1 (When receive)

TE bit

← 1 (When transmit)

Set RIE, TEIE and TIE bits

End

NOTES:

1. Write “0” after reading “1” to set the ORER bit to “0”.

SSER register

RE bit

← 0

TE bit

← 0

SSMR2 register

SCKS bit

← 1

Set SOOS bit

SSCRH register

Set MSS bit

SSMR register

CPHS bit

← 0

CPOS bit

← 0

Set MLS bit

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