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SH7708 Arkusz danych(PDF) 455 Page - Renesas Technology Corp |
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SH7708 Arkusz danych(HTML) 455 Page - Renesas Technology Corp |
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455 / 633 page ![]() 437 Table 16.6 Clock Timing (VCC = 3.3 ± 0.3 V, Ta = –20 to 75°C, Maximum External Bus Operating Frequency: 30 MHz) (cont) Item Symbol Min Max Unit Figure PLL synchronization settling time tPLL 100 — µs 16.8, 16.9, 16.10 IRL interrupt decision time (using RTC and in standby mode) tIRLSTB 100 — µs 16.10 Notes: 1. PLL circuit 2 in operation. 2. PLL circuit 1 not in operation. |
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