SH7708 datasheet(109/633 Pages) RENESAS

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4.5.2

General Exceptions

• TLB miss exception

 Conditions: Comparison of TLB addresses shows no address match

 Operations: The virtual address (32 bits) that caused the exception is set in TEA and the

corresponding virtual page number (22 bits) is set in PTEH (31–10). The ASID of PTEH

indicates the ASID at the time the exception occurred. The RC bit in MMUCR is

incremented by one for replacement.

The PC and SR of the instruction that generated the exception are saved to the SPC and SSR,

respectively. If the exception occurred during a read, H'040 is set in EXPEVT; if the exception

occurred during a write, H'060 is set in EXPEVT. The BL, MD and RB bits in SR are set to 1

and a branch occurs to PC = VBR + H'0400.

To speed up TLB miss processing, the offset differs from other exceptions.

• TLB invalid exception

 Conditions: Comparison of TLB addresses shows address match but V = 0

 Operations: The virtual address (32 bits) that caused the exception is set in TEA and the

corresponding virtual page number (22 bits) is set in PTEH (31–10). The ASID of PTEH

indicates the ASID at the time the exception occurred. The way that generated the

exception is set in the RC bits in MMUCR.

The PC and SR of the instruction that generated the exception are saved in the SPC and SSR,

respectively. If the exception occurred during a read, H'040 is set in EXPEVT; if the exception

occurred during a write, H'060 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1

and a branch occurs to PC = VBR + H'0100.

• Initial page write exception

 Conditions: A hit occurred to the TLB for a store access, but D = 0

This occurs for initial writes to the page registered by the load.

 Operations: The virtual address (32 bits) that caused the exception is set in TEA and the

corresponding virtual page number (22 bits) is set in PTEH (31–10). The ASID of PTEH

indicates the ASID at the time the exception occurred. The way that generated the

exception is set in MMUCR.RC.

The PC and SR of the instruction that generated the exception are saved to the SPC and SSR,

respectively. H'080 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a

branch occurs in PC = VBR + H'0100.

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