ADE5166 datasheet(133/148 Pages) AD

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ADE5166/ADE5169

Rev. 0 | Page 133 of 148

Table 154. SPI Configuration SFR 2 (SPIMOD2, Address 0xE9)

Bit

Mnemonic

Default

Description

SPICONT

Master mode, SPI continuous transfer mode enable bit.

SPICONT

Result

The SPI interface stops after one byte is transferred and SS is deasserted. A new data transfer can

be initiated after a stalled period.

The SPI interface continues to transfer data until no valid data is available in the SPI2CTx SFR. SS

remains asserted until the SPI2CTx SFR and the transmit shift registers are empty.

SPIEN

SPI interface enable bit.

SPIEN

Result

The SPI interface is disabled.

The SPI interface is enabled.

SPIODO

SPI open-drain output configuration bit.

SPIODO

Result

Internal pull-up resistors are connected to the SPI outputs.

The SPI outputs are open drain and need external pull-up resistors. The pull-up voltage should

not exceed the specified operating voltage.

SPIMS_b

SPI master mode enable bit.

SPIMS_b

Result

The SPI interface is defined as a slave.

The SPI interface is defined as a master.

SPICPOL

SPI clock polarity configuration bit (see Figure 108).

SPICPOL

Result

The default state of SCLK is low, and the first SCLK edge is rising. Depending on the SPICPHA bit,

the SPI data output changes state on the falling or rising edge of SCLK while the SPI data input is

sampled on the rising or falling edge of SCLK.

The default state of SCLK is high, and the first SCLK edge is falling. Depending on the SPICPHA

bit, the SPI data output changes state on the rising or falling edge of SCLK while the SPI data

input is sampled on the falling or rising edge of SCLK.

SPICPHA

SPI clock phase configuration bit (see Figure 108).

SPICPHA

Result

The SPI data output changes state when SS goes low at the second edge of SCLK and then every

two subsequent edges, whereas the SPI data input is sampled at the first SCLK edge and then

every two subsequent edges.

The SPI data output changes state at the first edge of SCLK and then every two subsequent

edges, whereas the SPI data input is sampled at the second SCLK edge and then every two

subsequent edges.

SPILSBF

Master mode, LSB first configuration bit.

SPILSBF

Result

The MSB of the SPI outputs is transmitted first.

The LSB of the SPI outputs is transmitted first.

TIMODE

Transfer and interrupt mode of the SPI interface.

TIMODE

Result

This bit must be set to 1 for proper operation.

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