PIC18F23K22-ESLASHSP datasheet(116/496 Pages) MICROCHIP

116 / 496 page

PIC18(L)F2X/4XK22

DS41412C-page 116

Preliminary

 2010 Microchip Technology Inc.

INTCON2: INTERRUPT CONTROL 2 REGISTER

R/W-1

U-0

R/W-1

U-0

R/W-1

RBPU

INTEDG0

INTEDG1

INTEDG2

—TMR0IP

—RBIP

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

RBPU: PORTB Pull-up Enable bit

1 = All PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled provided that the pin is an input and the corresponding WPUB bit is

set.

bit 6

INTEDG0: External Interrupt 0 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 5

INTEDG1: External Interrupt 1 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 4

INTEDG2: External Interrupt 2 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 3

Unimplemented: Read as ‘0’

bit 2

TMR0IP: TMR0 Overflow Interrupt Priority bit

1 = High priority

0 = Low priority

bit 1

Unimplemented: Read as ‘0’

bit 0

RBIP: RB Port Change Interrupt Priority bit

1 = High priority

0 = Low priority

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit. User software should ensure

the appropriate interrupt flag bits are clear

prior to enabling an interrupt. This feature

allows for software polling.

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