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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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IO130PDB3V2 Arkusz danych(PDF) 132 Page - Microsemi Corporation |
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IO130PDB3V2 Arkusz danych(HTML) 132 Page - Microsemi Corporation |
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132 / 212 page  Military ProASIC3/EL DC and Switching Characteristics 2-118 Revision 3 Timing Characteristics Table 2-191 • Register Delays Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V for A3PE600L and A3PE3000L Parameter Description –1 Std. Units tCLKQ Clock-to-Q of the Core Register 0.76 0.90 ns tSUD Data Setup Time for the Core Register 0.59 0.70 ns tHD Data Hold Time for the Core Register 0.00 0.00 ns tSUE Enable Setup Time for the Core Register 0.63 0.74 ns tHE Enable Hold Time for the Core Register 0.00 0.00 ns tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.55 0.65 ns tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.55 0.65 ns tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 0.00 ns tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.31 0.36 ns tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 0.00 ns tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.31 0.36 ns tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.30 0.34 ns tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.30 0.34 ns tCKMPWH Clock Minimum Pulse Width HIGH for the Core Register 0.56 0.64 ns tCKMPWL Clock Minimum Pulse Width LOW for the Core Register 0.56 0.64 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. |
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