AM79C978VCSLASHW datasheet(179/261 Pages) AMD

179 / 261 page

Am79C978

179

1 Mbps HomePNA PHY Internal Registers

The registers of the HomePNA PHY are accessible via

the internal MII interface. This interface uses the MII

Control, Address, and Data Registers (BCR32,

BCR33, and BCR34) in the integrated PCnet controller

to control and communicate to the HomePNA PHY via

the MDC and MDIO signals.

See Table 46 through Table 63.

HPR0: HomePNA PHY MII Control (Register 0)

Table 46.

HPR0: HomePNA PHY MII Control (Register 0)

Bits

Mnemonic

Description

Read/

Write

Default

Hex

Soft

Reset

MII_CONTROL

RESET

1 = RESET

0 = Normal operation

** Self Clearing

R/W

Loopback

1 = MII Loopback enabled

0 = MII Loopback disabled

R/W

Speed Selection

0 = 10 Mbps

Auto-Negotiation Enabled

1 = Enabled

0 = Disabled

R/W

Power Down

1 = Power down

0 = Normal operation

(This bit is mirrored in PHY Control bit 4)

R/W

Isolate

1 = Electrically isolate PHY from MII

0 = Normal operation

R/W

Restart Auto-Negotiation

1 = Restart Auto-Negotiation

0 = Normal operation

** Self Clearing

R/W

Duplex Mode

1 = Full-Duplex (for test purposes only)

0 = Half-Duplex

R/W

Collision Test

0 = Disable COL test signal

R/W

6:0

Reserved

Write as 0, Ignore Read

R/W

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