AM79C978VCSLASHW datasheet(129/261 Pages) AMD

129 / 261 page

Am79C978

129

15-0

CRBAU

Contains the upper 16 bits of the

current receive buffer address at

which the Am79C978 controller

will store incoming frame data.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR20: Current Transmit Buffer Address Lower

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

CXBAL

Contains the lower 16 bits of the

current transmit buffer address

from which the Am79C978 con-

troller is transmitting.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR21: Current Transmit Buffer Address Upper

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

CXBAU

Contains the upper 16 bits of the

current transmit buffer address

from which the Am79C978 con-

troller is transmitting.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR22: Next Receive Buffer Address Lower

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

NRBAL

Contains the lower 16 bits of the

next receive buffer address to

which the Am79C978 controller

will store incoming frame data.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR23: Next Receive Buffer Address Upper

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

NRBAU

Contains the upper 16 bits of the

next receive buffer address to

which the Am79C978 controller

will store incoming frame data.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR24: Base Address of Receive Ring Lower

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

BADRL

Contains the lower 16 bits of the

base address of the Receive

Ring.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR25: Base Address of Receive Ring Upper

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

BADRU

Contains the upper 16 bits of the

base address of the Receive

Ring.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR26: Next Receive Descriptor Address Lower

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

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