AM8530 datasheet(174/194 Pages) AMD

Numer części	AM8530

Szczegółowy opis	Serial Communications Controller

PDF	194 Pages

Scroll/Zoom	100%

Producent	AMD [Advanced Micro Devices]

Strona internetowa	http://www.amd.com

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174 / 194 page

SCC Application Notes

AMD

7–25

DTACK

PAL OUTPUTS:

Figure 7–15. PAL Timing

7.5.4

The 68000 and Am8530H with Interrupts via a PAL

Device

This example shows how a Programmable Array Logic (PAL) device simplifies the task of

interrupt generation compared to the MSI implementation. The block diagram for the in-

terface via a PAL device is shown in Figure 7–14. The timing diagram (Figure 7–15) illus-

trates the Interrupt Acknowledge cycle. As in the other designs,

RD is generated during

Interrupt Acknowledge to place the vector on the bus.

The timing during register programming is not shown. The PAL device allows selection of

one or two Wait States by making W0 High or Low respectively. The table below shows

the appropriate number of Wait Sates as a function of CPU speed.

CPU Speed

Wait States

4 MHz

6 MHz

8 MHz

10 MHz

PAL device equations are shown in Figure 7–16.

AM8530 Arkusz danych(PDF) 174 Page - Advanced Micro Devices