STM32F412RG datasheet(120/193 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F412xE/G

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DocID028087 Rev 4

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 36 and

Table 58, respectively.

Unless otherwise specified, the parameters given in Table 58 are derived from tests

performed under the ambient temperature and VDD supply voltage conditions summarized

in Table 15.

Table 57. Output voltage characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

VOL(1)

1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 13.

and the sum of IIO (I/O ports and control pins) must not exceed IVSS.

Output low level voltage for an I/O pin

CMOS port(2)

IIO = +8 mA

2.7 V ≤VDD ≤3.6 V

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

-0.4

VOH(3)

3. The IIO current sourced by the device must always respect the absolute maximum rating specified in

Table 13 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.

Output high level voltage for an I/O pin

VDD–0.4

VOL (1) Output low level voltage for an I/O pin

TTL port(2)

IIO =+8 mA

2.7 V ≤VDD ≤3.6 V

-0.4

VOH (3) Output high level voltage for an I/O pin

2.4

VOL(1) Output low level voltage for an I/O pin

IIO = +20 mA

2.7 V ≤VDD ≤3.6 V

-1.3(4)

4. Guaranteed by characterization results, not tested in production.

VOH(3) Output high level voltage for an I/O pin

VDD–1.3(4)

VOL(1) Output low level voltage for an I/O pin

IIO = +6 mA

1.8 V ≤VDD ≤3.6 V

-0.4(4)

VOH(3) Output high level voltage for an I/O pin

VDD–0.4(4)

VOL(1) Output low level voltage for an I/O pin

IIO = +4 mA

1.7 V ≤VDD ≤3.6 V

-0.4(5)

5. Guaranteed by design, not tested in production.

VOH(3) Output high level voltage for an I/O pin

VDD–0.4(5)

Table 58. I/O AC characteristics(1)(2)

OSPEEDRy

[1:0] bit

value(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fmax(IO)out Maximum frequency(3)

CL = 50 pF, VDD ≥ 2.70 V

MHz

CL = 50 pF, VDD≥ 1.7 V

CL = 10 pF, VDD ≥ 2.70 V

CL = 10 pF, VDD ≥ 1.7 V

tf(IO)out/

tr(IO)out

Output high to low level fall

time and output low to high

level rise time

CL = 50 pF, VDD = 1.7 V to

3.6 V

100

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