PC87366 datasheet(137/240 Pages) NSC

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6.0 General-Purpose Input/Output (GPIO) Port (Continued)

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6.4.6

GPIO Event Enable Register (GPEVEN)

Location:

Device specific

Type:

R/W

6.4.7

GPIO Event Status Register (GPEVST)

Location:

Device specific

Type:

R/W1C

Bit

76543210

Name

Event Enable

Reset

00000000

Bit

Description

Event Enable. Bits 7-0 correspond to pins 7-0 respectively. Each bit enables system notiﬁcation triggering by

the corresponding GPIO pin. The bit has no effect on the corresponding Status bit in the GPST register.

0: IRQ generation by corresponding GPIO pin masked

1: IRQ generation by corresponding GPIO pin enabled

Bit

76543210

Name

Status

Reset

00000000

Bit

Description

Status. Bits 7-0 correspond to pins 7-0 respectively. Each bit is an edge detector that is set to 1 by the hardware

upon detection of an active edge (i.e. edge that matches the IRQ Polarity bit) on the corresponding GPIO pin.

This edge detection is independent of the Event Type or the Event Enable bit in the GPEVEN register. However,

the bit may reﬂect the event status for enabled, edge-trigger event sources. Writing 1 to the Status bit clears it

to 0.

0: No active edge detected since last cleared

1: Active edge detected

PC87366 Arkusz danych(PDF) 137 Page - National Semiconductor (TI)

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