TNETV1644ZDU6 datasheet(205/306 Pages) TI1

205 / 306 page

6.9.3

EMIFA Electrical Data/Timing

TMS320DM6437

Digital Media Processor

www.ti.com

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

Table 6-24. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module(1)

(see Figure 6-14 and Figure 6-15)

-7/-6/-5/-4

-L/-Q6/-Q5/-Q4

NO.

UNIT

MIN

NOM

MAX

READS and WRITES

tw(EM_WAIT)

Pulse duration, EM_WAIT assertion and deassertion

READS

tsu(EMDV-EMOEH)

Setup time, EM_D[7:0] valid before EM_OE high

th(EMOEH-EMDIV)

Hold time, EM_D[7:0] valid after EM_OE high

tsu(EMWAIT-

Setup time, EM_WAIT asserted before EM_OE high(2)

4E + 5

EMOEH)

WRITES

tsu(EMWAIT-

Setup time, EM_WAIT asserted before EM_WE high(2)

4E + 5

EMWEH)

(1)

E = SYSCLK3 period in ns for EMIFA. For example, when running the DSP CPU at 600 MHz, use E = 10 ns.

(2)

Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended

wait states. Figure 6-16 and Figure 6-17 describe EMIF transactions that include extended wait states inserted during the STROBE

phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where

the HOLD phase would begin if there were no extended wait cycles.

Submit Documentation Feedback

Peripheral Information and Electrical Specifications

205

TNETV1644ZDU6 Arkusz danych(PDF) 205 Page - Texas Instruments

TNETV1644ZDU6 Arkusz danych(HTML) 205 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Arkusz danych Pobierz

Link URL