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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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ST7DALIF2 Arkusz danych(PDF) 153 Page - STMicroelectronics |
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ST7DALIF2 Arkusz danych(HTML) 153 Page - STMicroelectronics |
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153 / 171 page  ST7DALIF2 Electrical characteristics 153/171 Figure 90. SPI slave timing diagram with CPHA=1 Figure 91. SPI master timing diagram Note: 1 Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 2 When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends of the I/O port configuration. SS INPUT CPHA=0 MOSI INPUT MISO OUTPUT CPHA=1 tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) ta(SO) tsu(SI) th(SI) MSB OUT BIT6 OUT LSB OUT see CPOL=0 CPOL=1 tsu(SS) th(SS) tdis(SO) th(SO) see note 2 note 2 tc(SCK) HZ tv(SO) MSB IN LSB IN BIT1 IN SS INPUT CPHA = 0 MOSI OUTPUT MISO INPUT CPHA = 0 CPHA = 1 CPHA = 1 tc(SCK) tw(SCKH) tw(SCKL) th(MI) tsu(MI) MSB IN MSB OUT BIT6 IN BIT6 OUT LSB OUT LSB IN See note 2 Seenote2 CPOL = 0 CPOL = 1 CPOL = 0 CPOL = 1 tr(SCK) tf(SCK) th(MO) tv(MO) |
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