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Hello, Please ask a question about SC453 Datasheet
# Example questions:
➢ What is the maximum peak output current (ipkh) of the high side driver (tg)?
➢ What is the typical voltage offset (vslpv-vdac) for the slp input when the slpv = 0.8v?
➢ What is the typical value for the input bias current (irefin) of the core comparator?
| Part No. | SC453 |
| Manufacturer | SEMTECH |
| Size | 315 Kbytes |
| Pages | 23 pages |
| Description | Portable, VID Programmed Single Phase Power Supply Controller |
I. Core Voltage & Current Regulation
️· DAC Output Voltage: The datasheet appears to specify a programmable output voltage via a DAC.
️· Current Limit: The IC has programmable current limits controlled by comparator circuitry (CL, CLRF) with settings dependent on the RHYS resistor value and the SLP state. Values range from around 15µA to 265µA.
️· Zero-Crossing Detection: Comparators monitor core voltage and signal zero-crossing conditions for powersaving features.
️· Current Limit Comparator: Input bias current is ±2µA.
II. Comparator Characteristics (Multiple Comparators: CMP, CL, Core)
️· Input Bias Current: Comparators generally have an input bias current around ±2µA (IREFIN, ICL).
️· Input Voltage Offset: Offset voltages vary depending on the comparator, ranging from ±1.5mV to ±5mV.
️· Hysteresis: Hysteresis is adjustable via external resistors (RHYS). Values range from around -13µA to 110µA.
III. High-Side Driver (TG)
️· Peak Output Current: 1.5A.
️· Output Resistance: Varies depending on voltage and current, between 0.7Ω and 4.2Ω.
️· Rise Time: 60ns (for CTG = 3nF, VBST-VDRN = 5V).
️· Fall Time: 36ns (for CTG = 3nF, VBST-VDRN = 5V).
IV. Sleep Functionality
️· Sleep Input Thresholds: Logic high (ViH_SLP) at 2V, logic low (ViL_SLP) at 0.8V.
V. General Parameters
️· DAC Settling time: Not specified in this extract
️· Boot Delay: 10-35µs.
️· BOOT delay time: 10-35µs.
Important Notes:
️· RHYS Resistor: Many of the comparator parameters (current limit, hysteresis) are *heavily* dependent on the value of an external resistor, RHYS.
️· SLP State: The state of the Sleep (SLP) signal affects certain parameters, particularly current limits and comparator settings.
️· Voltage & Load Dependence: Parameters like output resistance and switching times are affected by input voltage (VBST-VDRN) and the load capacitance (CTG).
️· Datasheet Completeness: This is an excerpt; the complete datasheet will have far more detail on all these parameters and more.
️· Test conditions: Read the test conditions for each parameter.
I. Core Voltage & Current Regulation
️· DAC Output Voltage: The datasheet appears to specify a programmable output voltage via a DAC.
️· Current Limit: The IC has programmable current limits controlled by comparator circuitry (CL, CLRF) with settings dependent on the RHYS resistor value and the SLP state. Values range from around 15µA to 265µA.
️· Zero-Crossing Detection: Comparators monitor core voltage and signal zero-crossing conditions for powersaving features.
️· Current Limit Comparator: Input bias current is ±2µA.
II. Comparator Characteristics (Multiple Comparators: CMP, CL, Core)
️· Input Bias Current: Comparators generally have an input bias current around ±2µA (IREFIN, ICL).
️· Input Voltage Offset: Offset voltages vary depending on the comparator, ranging from ±1.5mV to ±5mV.
️· Hysteresis: Hysteresis is adjustable via external resistors (RHYS). Values range from around -13µA to 110µA.
III. High-Side Driver (TG)
️· Peak Output Current: 1.5A.
️· Output Resistance: Varies depending on voltage and current, between 0.7Ω and 4.2Ω.
️· Rise Time: 60ns (for CTG = 3nF, VBST-VDRN = 5V).
️· Fall Time: 36ns (for CTG = 3nF, VBST-VDRN = 5V).
IV. Sleep Functionality
️· Sleep Input Thresholds: Logic high (ViH_SLP) at 2V, logic low (ViL_SLP) at 0.8V.
V. General Parameters
️· DAC Settling time: Not specified in this extract
️· Boot Delay: 10-35µs.
️· BOOT delay time: 10-35µs.
Important Notes:
️· RHYS Resistor: Many of the comparator parameters (current limit, hysteresis) are *heavily* dependent on the value of an external resistor, RHYS.
️· SLP State: The state of the Sleep (SLP) signal affects certain parameters, particularly current limits and comparator settings.
️· Voltage & Load Dependence: Parameters like output resistance and switching times are affected by input voltage (VBST-VDRN) and the load capacitance (CTG).
️· Datasheet Completeness: This is an excerpt; the complete datasheet will have far more detail on all these parameters and more.
️· Test conditions: Read the test conditions for each parameter.
| Part No. | SC453 |
| Manufacturer | SEMTECH |
| Size | 315 Kbytes |
| Pages | 23 pages |
| Description | Portable, VID Programmed Single Phase Power Supply Controller |
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