General Description
The SY100ELT23 is a dual differential PECL-to-TTL
translator. Because PECL (positive ECL) levels are
used, only +5V and ground are required. The small
outline 8-lead SOIC package and low skew, dual gate
design make the ELT23 ideal for applications that
require the translation of a clock or data signal.
The ELT23 is compatible with positive ECL 100K logic
levels.

Features
• 3.0 ns Typical Propagation Delay
• <300 ps Typical Within-Device Skew
• Differential PECL Inputs
• 24 mA TTL Outputs
• Flow-Through Pinouts
• Internal Input 50 kΩ Pull-Down Resistors
• Available in 8-Lead SOIC Package