General description
The LPC11D14 is a ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for
8/16-bit microcontroller applications, offering performance, low power, simple instruction
set and memory addressing together with reduced code size compared to existing 8/16-bit
architectures.
The LPC11D14 is a dual-chip module consisting of a LPC1114 single-chip microcontroller
combined with a PCF8576D Universal LCD driver in a low-cost 100-pin package. The
LCD driver provides 40 segments and supports from one to four backplanes. Display
overhead is minimized by an on-chip display RAM with auto-increment addressing.
The LPC11D14 operates at CPU frequencies of up to 50 MHz.
The peripheral complement of the LPC11D14 includes 32 kB of flash memory, 8 kB of
data memory, one Fast-mode Plus I2C-bus interface, one RS-485/EIA-485 UART, up to
two SPI interfaces with SSP features, four general purpose counter/timers, a 10-bit ADC,
and up to 42 general purpose I/O pins.
Remark: For a functional description of the LPC1114 microcontroller see the
LPC1111/12/13/14 data sheet. For a detailed description of the LCD driver see the
PCF8576D data sheet. Both data sheets are available on the NXP web site.

Features and benefits
 LCD driver
 40 segments.
 One to four backplanes.
 On-chip display RAM with auto-increment addressing.
 System:
 ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
 ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
 Serial Wire Debug.
 System tick timer.
 Memory:
 32 kB on-chip flash programming memory.
 8 kB SRAM.
 In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
 Digital peripherals:
 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors.
In addition, a configurable open-drain mode is supported.
 GPIO pins can be used as edge and level sensitive interrupt sources.
 High-current output driver (20 mA) on one pin.
 High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus.
 Four general purpose counter/timers with a total of four capture inputs and 13
match outputs.
 Programmable windowed WatchDog Timer (WDT).
 Analog peripherals:
 10-bit ADC with input multiplexing among 8 pins.
 Serial interfaces:
 UART with fractional baud rate generation, internal FIFO, and RS-485 support.
 Two SPI controllers with SSP features and with FIFO and multi-protocol
capabilities.
 I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a
data rate of 1 Mbit/s with multiple address recognition and monitor mode.
 Clock generation:
 12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used
as a system clock.
 Crystal oscillator with an operating range of 1 MHz to 25 MHz.
 Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.
 PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the system oscillator or the internal RC
oscillator.
 Clock output function with divider that can reflect the system oscillator clock, IRC
clock, CPU clock, and the Watchdog clock.
 Power control:
 Integrated PMU (Power Management Unit) to minimize power consumption during
Sleep, Deep-sleep, and Deep power-down modes.
 Power profiles residing in boot ROM allowing to optimize performance and
minimize power consumption for any given application through one simple function
call.
 Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.
 Processor wake-up from Deep-sleep mode via a dedicated start logic using up to
13 of the functional pins.
 Power-On Reset (POR).
 Brownout detect with four separate thresholds for interrupt and forced reset.
 Unique device serial number for identification.
 Single power supply (1.8 V to 3.6 V).
 Available as 100-pin LQFP100 package.