Features

• DisplayPort® (DP) ver.1.4a compliant receiver
 Link rate 1.62 / 2.7 / 5.4 / 8.1Gbps
 1, 2, or 4 lanes configuration
 AUX CH 1Mbps
 HPD_OUT
 Programmable receiver equalization
 TPS4 EQ Phase LT support
 Scrambling of main link data
 De-spreading of link frequency
 Video Stream Handling
■ RGB/ YCC 444/422/420 pixel format up to 16 bpc
 DPCD and CEC
■ DPCD data structure revision 1.4
■ CEC tunneling over AUX
 Audio stream handling
■ Non-HBR Compressed Formats
• 2/8 ch layouts
• Up to 192kHz sample rates
• Dolby Digital, Digital+, Atmos
■ HBR Audio Formats
• 8 ch layout
• Up to 1536kHz sample rates
• Dolby TrueHD, Atmos, DTS Master
■ LPCM Formats2/8/16/32 Ch
• Up to 192kHz sample rates
• 3D LPCM, speaker allocation & mapping
■ One Bit DSD Formats
• 2/8 ch
• Single & Double Rate
• 12288kHz sample rates
■ DST DSD Formats
• Single/Double rate
• Up to 22579.2kHz
• Audio InfoFrame/ ACM/ ISRC/ Audio
Metadata DI packets
• HDMI2.0b transmitter
 HDMI mode
■ DC-coupled output with source termination
■ 600 MHz maximum TMDS character clock
■ TMDS character-clock divide_by_4 mode
■ HPD_IN (5V Tolerant)
■ DDC CH (5V Tolerant)
■ Conversion to DVI output
 Scrambler for HDMI output
 Programmable signal amplitude
 Programmable pre-emphasis control
 Pixel format RGB / YCC 444/422/420
 Deep color up to 16 bits per color
 3D video timings
 CEC 2.0+ with snooping, tunneling
 SCDC read request handling
 Metadata handling
• HDMI 2.1 Features
 Through 6GHz TMDS Mode
 Supports 4k120Hz,4:2:0, 8bpc with Adaptive Sync
to VRR conversion
 Dynamic HDR Metadata through Extended
Metadata Packet
 Supports VRR, FVA, QMS, QFT, ALLM

Description

The MCDP5250 is an advanced DisplayPort1.4a to
HDMI2.0b protocol converter targeted primarily for
Mobile Notebook accessory and display applications.
This device functions as a DP to HDMI protocol
converter with an HDCP1.x/ HDCP2.x repeater
function.
The receiver in MCDP5250 supports all DP standard
data rates up to HBR3 (8.1Gbps/lane). The transmitter
supports TMDS data format up to 6.0Gbps/lane. The
side-band channel uses 1.0 Mbps Manchester-coded
AUX signaling for DP and DDC signaling up to 100
kbps for the HDMI interface.
In the protocol converter mode, MCDP5250 translates
a DP SST stream into DC coupled HDMI2.0b output.
The highest video timing supported in this mode is
4k2k60Hz RGB/YCC 444 or 4k2k120Hz in YCC 420-
pixel format. It supports both RGB 444 and
YCC444/422/420 video pixel encoding formats with a
color depth up to 16 bpc (bits per component or 48 bits
per pixel). The MCDP5250 also has a pixel processing
unit capable of video color space conversion from
RGB444 to YCC444 with bit depth expansion and pixel
encoding format conversion from YCC444 to
YCC422/420. It also supports advanced dithering
function to truncate the pixel bit depth to the precision
of the connected sink device. Pixel format conversion
along with horizontal blanking expansion improves
interoperability and smooth rendering of video from
mobile PC and tablets on legacy TVs. Besides,
MCDP5250 also supports HDMI CEC tunneling over
DP AUX channel for remote control pass-through, one
touch control of the connected devices in a CE system.
The MCDP5250 processes High Dynamic Range
(HDR) video content specified in BT601, BT709,
BT2020 or in the Adobe RGB colorimetry format with
the appropriate metadata conversion from DP to HDMI
standard. It also offers secure reception and
transmission of high bandwidth digital audio and video
content with HDCP1.x or HDCP2.x content protection.
MCDP5250 functions as an HDCP1.x and HDCP2.x
repeater between the DP source and DP or HDMI sink.
The MCDP5250 uses an external crystal of 25MHz as
a reference clock for its operation. It has a 300MHz
ARM Cortex M3 CPU with on-chip memories for
storing data and code execution. The peripheral
subsystem includes SPI, UART (debug only), and I2C
master and slave interfaces. An internal Power-On
Reset (POR) circuit senses the voltage on the reset
input and provides the chip reset during system powerup.
The MCDP5250 uses an external 16Mbit SPI flash
memory for storing the RSA-2048 signed application
firmware with fail-safe recovery. At boot up, the CPU
goes through a secure boot process authenticating the
application code image stored in the SPI flash. It
supports both standard mode and quad mode
operation. A firmware update of the SPI flash is done
securely through the DP AUX_CH or I2C host
interface (Secure In-System-Programming).

Applications Information

The target applications of MCDP5250 are the notebook, tablet accessories i.e., adapters (dongles), docking stations
and other AV accessories.
Adapter (Dongle) Application
In a dongle topology the MCDP5250 is part of the source side adaptor that plugs into a DP source device via a
DisplayPort connector at the upstream facing port. In a typical DP-to-HDMI dongle application, MCDP5250 functions
as a system master and operates as a protocol converter.