Description
The 9DBV0641 is a member of Renesas’ 1.8V
Very-Low-Power (VLP) PCIe family. It has integrated output
terminations providing Zo = 100 for direct connection to
100 transmission lines. The device has 6 output enables for
clock management and 3 selectable SMBus addresses.

Features/Benefits
• Direct connection to 100 transmission lines; saves 24
resistors compared to standard PCIe devices
• 55mW typical power consumption in PLL mode; minimal
power consumption
• Outputs can optionally be supplied from any voltage
between 1.05 and 1.8V; maximum power savings
• OE# pins; support DIF power management
• HCSL compatible differential input; can be driven by
common clock sources
• Spread Spectrum tolerant; allows reduction of EMI
• Programmable Slew rate for each output; allows tuning for
various line lengths
• Programmable output amplitude; allows tuning for various
application environments
• Pin/software selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
• Outputs blocked until PLL is locked; clean system start-up
• Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
• 3.3V tolerant SMBus interface works with legacy controllers
• Space saving 5 × 5mm 40-VFQFPN; minimal board space
• 3 selectable SMBus addresses; multiple devices can easily
share an SMBus segment