Features
Generates up to two independent output frequencies
High-performance, low-phase noise PLL, < 0.7ps RMS
typical phase jitter on outputs:
– PCIe Gen1–3 compliant clock capability
– USB 3.0 compliant clock capability
– 1GbE and 10GbE
Two fractional output dividers (FODs)
Independent spread spectrum capability on each output
pair
Two banks of internal non-volatile in-system programmable
or factory programmable OTP memory
I2C serial programming interface
One reference LVCMOS output clock
Two universal output pairs:
– Each configurable as one differential output pair or two
LVCMOS outputs
I/O Standards:
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
– Differential I/Os: LVPECL, LVDS and HCSL
Input frequency ranges:
– LVDS, LVPECL, HCSL differential clock input (CLKIN,
CLKINB) – 1MHz to 350MHz
Output frequency ranges:
– LVCMOS clock outputs: 1MHz to 200MHz
– LVDS, LVPECL, HCSL differential clock outputs: 1MHz
to 350MHz
Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
each output pair
Redundant clock inputs with manual switchover
Programmable loop bandwidth
Programmable output to output skew
Programmable slew rate control
Individual output enable/disable
Power-down mode
1.8V, 2.5V or 3.3V core VDDD, VDDA
4 x 4 mm 24-LGA package
-40° to +85°C industrial temperature operation