Six selectable 100MHz, 125MHz, 156.25MHz and 312.5MHz
clocks for sRIO, XAUI, SGMII and HCSL interface levels
One 125MHz RGMII clock (QG), LVCMOS/LVTTL interface levels
One 50MHz processor core clock (QF), LVCMOS/LVTTL
interface levels
Two 25MHz QREF clocks, LVCMOS/LVTTL interface levels,
15 output impedance
Selectable external crystal or differential (single-ended) input
source
Crystal oscillator interface designed for 25MHz, parallel
resonant crystal
Differential CLK, nCLK input pair that can accept: LVPECL, LVDS,
LVHSTL, HCSL input levels
Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
Full 3.3V or mixed 3.3V core/2.5V output supply modes, (RGMII
output and QREF outputs)
Full 3.3V output supply mode, (HCSL and core clock outputs)
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging