FEATURES
RISC M•CORE MCU
• 32-bit load/store RISC architecture
• Fixed 16-bit instruction length
• 16-entry 32-bit general-purpose register file
• 32-bit internal address and data buses
• Efficient four-stage, fully interlocked execution pipeline
• Single-cycle execution for most instructions, two cycles for branches and memory
accesses
• Special branch, byte, and bit manipulation instructions
• Support for byte, half-word, and word memory accesses
• Fast interrupt support via vectoring/auto-vectoring and a 16-entry dedicated
alternate register file