The MPC99J93 is a PLL clock driver designed specifically for redundant clock
tree designs. The device receives two differential LVPECL clock signals from
which it generates five new differential LVPECL clock outputs. Two of the output
pairs regenerate the input signals frequency and phase while the other three
pairs generate 2x, phase aligned clock outputs.
Features
• Fully Integrated PLL
• Intelligent Dynamic Clock Switch
• LVPECL Clock Outputs
• LVCMOS Control I/O
• 3.3-V Operation
• 32-Lead LQFP Packaging, Pb-Free
Functional Description
The MPC99J93 Intelligent Dynamic Clock Switch (IDCS) circuit continuously
monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or
LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that
CLK is the primary clock, the IDCS will switch to the good secondary clock and
phase/frequency alignment will occur with minimal output phase disturbance.
The typical phase bump caused by a failed clock is eliminated. (See Applications
Information section).