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NPIC6C596D-Q100 Arkusz danych (PDF) - Nexperia B.V. All rights reserved

NPIC6C596D-Q100 Datasheet PDF - Nexperia B.V. All rights reserved
Numer części NPIC6C596D-Q100
Pobierz  NPIC6C596D-Q100 Pobierz
Rozmiar pliku   281.5 Kbytes
Page   18 Pages
Producent  NEXPERIA [Nexperia B.V. All rights reserved]
Strona internetowa  https://www.nexperia.com/
Logo NEXPERIA - Nexperia B.V. All rights reserved
Szczegółowy opis Power logic 8-bit shift register; open-drain outputs

NPIC6C596D-Q100 Datasheet (PDF)

Go To PDF Page Pobierz Arkusz danych
NPIC6C596D-Q100 Datasheet PDF - Nexperia B.V. All rights reserved

Numer części NPIC6C596D-Q100
Pobierz  NPIC6C596D-Q100 Click to download

Rozmiar pliku   281.5 Kbytes
Page   18 Pages
Producent  NEXPERIA [Nexperia B.V. All rights reserved]
Strona internetowa  https://www.nexperia.com/
Logo NEXPERIA - Nexperia B.V. All rights reserved
Szczegółowy opis Power logic 8-bit shift register; open-drain outputs

NPIC6C596D-Q100 Arkusz danych (HTML) - Nexperia B.V. All rights reserved


NPIC6C596D-Q100 Szczegóły Produktu

1. General description
The NPIC6C596-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register
and open-drain outputs. Both the shift and storage register have separate clocks. The device
features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous
reset MR input. A LOW on MR resets both the shift register and storage register. Data is shifted
on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to
the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected
together, the shift register is always one clock pulse ahead of the storage register. To provide
additional hold time in cascaded applications, the serial output QS7 is clocked out on the falling
edge of SHCP. Data in the storage register drives the gate of the output extended-drain NMOS
(EDNMOS) transistor whenever the output enable input (OE) is LOW. A HIGH on OE causes the
outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the
state of the registers.
The open-drain outputs are 33 V/100 mA continuous current extended-drain NMOS transistors
designed for use in systems that require moderate load power such as LEDs. Integrated voltage
clamps in the outputs provide protection against inductive transients making the device suitable for
power driver applications such as relays, solenoids and other low-current or medium-voltage loads.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits
• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +125 °C
• Low RDSon
• Eight Power EDNMOS transistor outputs of 100 mA continuous current
• 250 mA current limit capability
• Output clamping voltage 33 V
• 30 mJ avalanche energy capability
• Enhanced cascading for multiple stages
• All registers cleared with single input
• Low power consumption
• ESD protection:
• HBM AEC-Q100-002 revision D exceeds 2500 V
• CDM AEC-Q100-011 revision B exceeds 1000 V
• DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of
solder joints

3. Applications
• LED sign
• Graphic status panel
• Fault status indicator




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