Features
The main features of the Core are:
• High-speed, 16-bit processing with the same programming model and instruction set as the
Motorola 68HC12 CPU
• Full 16-bit data paths for efficient arithmetic operation and high-speed mathematical execution
• Allows instructions with odd byte counts, including many single-byte instructions for more
efficient use of program memory space
• Three stage instruction queue to buffer program information for more efficient CPU execution
• Extensive set of indexed addressing capabilities including:
– Using the stack pointer as an indexing register in all indexed operations
– Using the program counter as an indexing register in all but auto increment/decrement mode
– Accumulator offsets using A, B or D accumulators
– Automatic index pre-decrement, pre-increment, post-decrement and post-increment (by -8 to
+8)
– 5-bit, 9-bit or 16-bit signed constant offsets
– 16-bit offset indexed-indirect and accumulator D offset indexed-indirect addressing
• Provides 2 to 122 I bit maskable interrupt vectors, 1 X bit maskable interrupt vector, 2 nonmaskable
CPU interrupt vectors and 3 reset vectors
• Optional register configurable highest priority I bit maskable interrupt
• On-chip memory and peripheral block interfacing with internal memory expansion capability and
external data chip select
• Configurable system memory and mapping options
• External Bus Interface (8-bit or 16-bit, multiplexed or non-multiplexed)
• Multiple modes of operation
• Hardware breakpoint support for forced or tagged breakpoints with two modes of operation:
– Dual Address Mode to match on either of two addresses
– Full Breakpoint Mode to match on address and data combination
• Single-wire background debug system implemented in on-chip hardware
• Secured mode of operation
• Fully synthesizable design
• Single Core clock operation
• Full Mux-D scan test implementation