Features
◆ 128K x 36, 256K x 18 memory configurations
◆ Supports high performance system speed - 166 MHz (x36)
(3.5 ns Clock-to-Data Access)
◆ ZBTTM Feature - No dead cycles between write and read
cycles
◆ Internally synchronized output buffer enable eliminates the
need to control OE
◆ Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
◆ Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
◆ Single R/W (READ/WRITE) control pin