Recommended Application:
DDR Clock Driver
Product Description/Features:
• Low skew, low jitter PLL clock driver
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• With bypass mode mux
• Operating frequency 60 to 210 MHz
• AC Coupled (Universal) CLK inputs:
- 400 mV switching amplitude
- (LVTTL, LVPELL, LVDS, LVCMOS) standards
translation to SSTL2
Switching Characteristics:
• CYCLE - CYCLE jitter: <60ps
• OUTPUT - OUTPUT skew: <60ps
• Period jitter: ±30ps
• DUTY CYCLE: 49.5% - 50.5%