FEATURES
· FUNCTIONS
• Instruction cycle: 30 ns (MIN.) with 33 MHz clock
• Dual load/store
• Hardware loop function
• Conditional execution
• Executes product-sum operation in one instruction cycle
· PROGRAMMING
• 16 bits ´ 16 bits + 40 bits ® 40 bits multiply accumulator
• 8 general registers (40 bits each)
• 8 ROM/RAM data pointer: each data memory area has 4 registers
• 10 source interrupts (external: 4, internal: 6)
• 3 operand instructions (example: R0 = R0 +R1L*R2L)
• Nonpipeline on execution stage
· MEMORY AREAS
• Program memory area: 64K words ´ 32 bits
• Two independent data memory areas: 64K words ´ 16 bits (X/Y memory)
· ON-CHIP PERIPHERAL
• I/O port: 4 bits
• Serial I/O (16 bits): 2 channels
· CMOS
· +5 V single power supply